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MarBle
FL2K Liberation
Commits
29ac0fa8
Commit
29ac0fa8
authored
May 29, 2019
by
MarBle
Browse files
preliminary finish of schematic
parent
5585691a
Changes
4
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img/fl2k.xcf
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src/fl2k-cache.lib
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@@ -221,37 +221,68 @@ ENDDEF
# Interface_USB_FL2000
#
DEF Interface_USB_FL2000 U 0 20 Y Y 1 F N
F0 "U" -
6
00 10
5
0 50 H V L CNN
F1 "Interface_USB_FL2000"
6
00 10
5
0 50 H V R CNN
F2 "Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm_ThermalVias" 0 -400 50 H I C CNN
F0 "U" -
5
00 1
6
00 50 H V L CNN
F1 "Interface_USB_FL2000"
7
00 1
6
00 50 H V R CNN
F2 "Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm_ThermalVias"
-10
0 -400 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -600 1000 600 -900 0 1 0 f
X ~CS~ 10 700 600 100 L 50 50 1 1 O
X ~WP~ 11 700 500 100 L 50 50 1 1 B
X ~HOLD~ 12 700 400 100 L 50 50 1 1 B
X MOSI 13 700 800 100 L 50 50 1 1 B
X NC 14 -200 -1000 100 U 50 50 1 1 N N
X XO 16 -700 -400 100 R 50 50 1 1 O
X XI 17 -700 -500 100 R 50 50 1 1 I
X D+ 18 -700 400 100 R 50 50 1 1 B
X D- 19 -700 500 100 R 50 50 1 1 B
X SSTX- 24 -700 200 100 R 50 50 1 1 O
X SSTX+ 25 -700 100 100 R 50 50 1 1 O
X SSRX- 27 -700 -100 100 R 50 50 1 1 I
X SSRX+ 28 -700 -200 100 R 50 50 1 1 I
X ID3_SCL 29 700 -700 100 L 50 50 1 1 O
X ID1_SDA 30 700 -800 100 L 50 50 1 1 B
X MISO 31 700 900 100 L 50 50 1 1 B
X NC 32 -300 -1000 100 U 50 50 1 1 N N
X NC 35 -400 -1000 100 U 50 50 1 1 N N
X GND 42 0 -1000 100 U 50 50 1 1 W
X R 51 700 -300 100 L 50 50 1 1 O
X G 53 700 -400 100 L 50 50 1 1 O
X B 54 700 -500 100 L 50 50 1 1 O
X GND 55 0 -1000 100 U 50 50 1 1 W N
X NC 7 -100 -1000 100 U 50 50 1 1 N N
X SCK 9 700 700 100 L 50 50 1 1 O
S -900 1100 800 -1950 0 1 0 f
X VDD 1 100 1200 100 D 50 50 1 1 W
X ~CS~ 10 900 500 100 L 50 50 1 1 O
X ~WP~ 11 900 400 100 L 50 50 1 1 B
X ~HOLD~ 12 900 300 100 L 50 50 1 1 B
X MOSI 13 900 700 100 L 50 50 1 1 B
X NC 14 -200 -2050 100 U 50 50 1 1 N N
X VDDA 15 -200 1200 100 D 50 50 1 1 W
X XO 16 -1000 -400 100 R 50 50 1 1 O
X XI 17 -1000 -500 100 R 50 50 1 1 I
X D+ 18 -1000 400 100 R 50 50 1 1 B
X D- 19 -1000 500 100 R 50 50 1 1 B
X VDDA 2 0 1200 100 D 50 50 1 1 W
X VDD_USB 20 -1000 800 100 R 50 50 1 1 W
X R_12k_GND 21 -1000 -1100 100 R 50 50 1 1 P
X C_2n_GND 22 -1000 -1900 100 R 50 50 1 1 P
X C_5u_GND 23 -1000 -1700 100 R 50 50 1 1 P
X SSTX- 24 -1000 200 100 R 50 50 1 1 O
X SSTX+ 25 -1000 100 100 R 50 50 1 1 O
X VDDA_USB 26 -1000 700 100 R 50 50 1 1 W
X SSRX- 27 -1000 -100 100 R 50 50 1 1 I
X SSRX+ 28 -1000 -200 100 R 50 50 1 1 I
X ID3_SCL 29 900 -1000 100 L 50 50 1 1 O
X HSYNC 3 900 -700 100 L 50 50 1 1 O
X ID1_SDA 30 900 -1100 100 L 50 50 1 1 B
X MISO 31 900 800 100 L 50 50 1 1 B
X NC 32 -300 -2050 100 U 50 50 1 1 N N
X CABLE_DETECT 33 900 -1300 100 L 50 50 1 1 I
X R_DNP_VCC 33 -1000 -700 100 R 50 50 1 1 P
X NC 35 -400 -2050 100 U 50 50 1 1 N N
X VDDA 36 -300 1200 100 D 50 50 1 1 W
X VDD 37 300 1200 100 D 50 50 1 1 W
X VDD 38 400 1200 100 D 50 50 1 1 W
X VDDA 39 -400 1200 100 D 50 50 1 1 W
X VSYNC 4 900 -800 100 L 50 50 1 1 O
X VDD 40 500 1200 100 D 50 50 1 1 W
X VDDA_VGA 41 900 -100 100 L 50 50 1 1 W
X GND 42 0 -2050 100 U 50 50 1 1 W
X VDD 43 600 1200 100 D 50 50 1 1 W
X VDDA 44 -500 1200 100 D 50 50 1 1 W
X VDDA 45 -600 1200 100 D 50 50 1 1 W
X VDD 46 700 1200 100 D 50 50 1 1 W
X VDDA 47 -700 1200 100 D 50 50 1 1 W
X C_100n_GND 48 -1000 -1500 100 R 50 50 1 1 P
X VDD_VGA_ref 49 900 0 100 L 50 50 1 1 I
X VDDA 5 -100 1200 100 D 50 50 1 1 W
X R_5.6k_GND 50 -1000 -900 100 R 50 50 1 1 P
X R 51 900 -300 100 L 50 50 1 1 O
X VDD_VGA 52 900 100 100 L 50 50 1 1 W
X G 53 900 -400 100 L 50 50 1 1 O
X B 54 900 -500 100 L 50 50 1 1 O
X GND 55 0 -2050 100 U 50 50 1 1 W N
X VDDA 56 -800 1200 100 D 50 50 1 1 W
X R_10k_GND 6 -1000 -1300 100 R 50 50 1 1 P
X NC 7 -100 -2050 100 U 50 50 1 1 N N
X VDD 8 200 1200 100 D 50 50 1 1 W
X SCK 9 900 600 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
...
...
@@ -369,6 +400,21 @@ X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3VA
#
DEF power_+3.3VA #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3VA" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3.3VA 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
...
...
@@ -412,21 +458,6 @@ X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VBUS
#
DEF power_VBUS #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VBUS" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VBUS 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VDD
#
DEF power_VDD #PWR 0 0 Y Y 1 F P
...
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src/fl2k.kicad_pcb
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src/fl2k.sch
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