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Commit 93849459 authored by MarBle's avatar MarBle
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cleanup and reordering

parent f587ce6c
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.gitignore
View file @ 93849459
......@@ -10,6 +10,7 @@
_autosave-*
*.tmp
*-rescue.lib
*-rescue.dcm
*-save.pro
*-save.kicad_pcb
fp-info-cache
......@@ -25,3 +26,5 @@ fp-info-cache
*.xml
*.csv
sym-lib-table
src/fl2k-cache.lib
View file @ 93849459
......@@ -218,74 +218,6 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Interface_USB_FL2000
#
DEF Interface_USB_FL2000 U 0 20 Y Y 1 F N
F0 "U" -500 1600 50 H V L CNN
F1 "Interface_USB_FL2000" 700 1600 50 H V R CNN
F2 "Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm_ThermalVias" -100 -400 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -900 1100 800 -1950 0 1 0 f
X VDD 1 100 1200 100 D 50 50 1 1 W
X ~CS~ 10 900 500 100 L 50 50 1 1 O
X ~WP~ 11 900 400 100 L 50 50 1 1 B
X ~HOLD~ 12 900 300 100 L 50 50 1 1 B
X MOSI 13 900 700 100 L 50 50 1 1 B
X NC 14 -200 -2050 100 U 50 50 1 1 N N
X VDDA 15 -200 1200 100 D 50 50 1 1 W
X XO 16 -1000 -400 100 R 50 50 1 1 O
X XI 17 -1000 -500 100 R 50 50 1 1 I
X D+ 18 -1000 400 100 R 50 50 1 1 B
X D- 19 -1000 500 100 R 50 50 1 1 B
X VDDA 2 0 1200 100 D 50 50 1 1 W
X VDD_USB 20 -1000 800 100 R 50 50 1 1 W
X R_12k_GND 21 -1000 -1100 100 R 50 50 1 1 P
X C_2n_GND 22 -1000 -1900 100 R 50 50 1 1 P
X C_5u_GND 23 -1000 -1700 100 R 50 50 1 1 P
X SSTX- 24 -1000 200 100 R 50 50 1 1 O
X SSTX+ 25 -1000 100 100 R 50 50 1 1 O
X VDDA_USB 26 -1000 700 100 R 50 50 1 1 W
X SSRX- 27 -1000 -100 100 R 50 50 1 1 I
X SSRX+ 28 -1000 -200 100 R 50 50 1 1 I
X ID3_SCL 29 900 -1000 100 L 50 50 1 1 O
X HSYNC 3 900 -700 100 L 50 50 1 1 O
X ID1_SDA 30 900 -1100 100 L 50 50 1 1 B
X MISO 31 900 800 100 L 50 50 1 1 B
X NC 32 -300 -2050 100 U 50 50 1 1 N N
X CABLE_DETECT 33 900 -1300 100 L 50 50 1 1 I
X R_DNP_VCC 33 -1000 -700 100 R 50 50 1 1 P
X NC 35 -400 -2050 100 U 50 50 1 1 N N
X VDDA 36 -300 1200 100 D 50 50 1 1 W
X VDD 37 300 1200 100 D 50 50 1 1 W
X VDD 38 400 1200 100 D 50 50 1 1 W
X VDDA 39 -400 1200 100 D 50 50 1 1 W
X VSYNC 4 900 -800 100 L 50 50 1 1 O
X VDD 40 500 1200 100 D 50 50 1 1 W
X VDDA_VGA 41 900 -100 100 L 50 50 1 1 W
X GND 42 0 -2050 100 U 50 50 1 1 W
X VDD 43 600 1200 100 D 50 50 1 1 W
X VDDA 44 -500 1200 100 D 50 50 1 1 W
X VDDA 45 -600 1200 100 D 50 50 1 1 W
X VDD 46 700 1200 100 D 50 50 1 1 W
X VDDA 47 -700 1200 100 D 50 50 1 1 W
X C_100n_GND 48 -1000 -1500 100 R 50 50 1 1 P
X VDD_VGA_ref 49 900 0 100 L 50 50 1 1 I
X VDDA 5 -100 1200 100 D 50 50 1 1 W
X R_5.6k_GND 50 -1000 -900 100 R 50 50 1 1 P
X R 51 900 -300 100 L 50 50 1 1 O
X VDD_VGA 52 900 100 100 L 50 50 1 1 W
X G 53 900 -400 100 L 50 50 1 1 O
X B 54 900 -500 100 L 50 50 1 1 O
X GND 55 0 -2050 100 U 50 50 1 1 W N
X VDDA 56 -800 1200 100 D 50 50 1 1 W
X R_10k_GND 6 -1000 -1300 100 R 50 50 1 1 P
X NC 7 -100 -2050 100 U 50 50 1 1 N N
X VDD 8 200 1200 100 D 50 50 1 1 W
X SCK 9 900 600 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# Memory_Flash_AT25SF081-SSHD-X
#
DEF Memory_Flash_AT25SF081-SSHD-X U 0 20 Y Y 1 F N
......@@ -384,6 +316,74 @@ X D 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# fl2k-rescue_FL2000-Interface_USB
#
DEF fl2k-rescue_FL2000-Interface_USB U 0 20 Y Y 1 F N
F0 "U" -500 1600 50 H V L CNN
F1 "fl2k-rescue_FL2000-Interface_USB" 700 1600 50 H V R CNN
F2 "Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm_ThermalVias" -100 -400 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -900 1100 800 -1950 0 1 0 f
X VDD 1 100 1200 100 D 50 50 1 1 W
X ~CS~ 10 900 500 100 L 50 50 1 1 O
X ~WP~ 11 900 400 100 L 50 50 1 1 B
X ~HOLD~ 12 900 300 100 L 50 50 1 1 B
X MOSI 13 900 700 100 L 50 50 1 1 B
X NC 14 -200 -2050 100 U 50 50 1 1 N N
X VDDA 15 -200 1200 100 D 50 50 1 1 W
X XO 16 -1000 -400 100 R 50 50 1 1 O
X XI 17 -1000 -500 100 R 50 50 1 1 I
X D+ 18 -1000 400 100 R 50 50 1 1 B
X D- 19 -1000 500 100 R 50 50 1 1 B
X VDDA 2 0 1200 100 D 50 50 1 1 W
X VDD_USB 20 -1000 800 100 R 50 50 1 1 W
X R_12k_GND 21 -1000 -1100 100 R 50 50 1 1 P
X C_2n_GND 22 -1000 -1900 100 R 50 50 1 1 P
X C_5u_GND 23 -1000 -1700 100 R 50 50 1 1 P
X SSTX- 24 -1000 200 100 R 50 50 1 1 O
X SSTX+ 25 -1000 100 100 R 50 50 1 1 O
X VDDA_USB 26 -1000 700 100 R 50 50 1 1 W
X SSRX- 27 -1000 -100 100 R 50 50 1 1 I
X SSRX+ 28 -1000 -200 100 R 50 50 1 1 I
X ID3_SCL 29 900 -1000 100 L 50 50 1 1 O
X HSYNC 3 900 -700 100 L 50 50 1 1 O
X ID1_SDA 30 900 -1100 100 L 50 50 1 1 B
X MISO 31 900 800 100 L 50 50 1 1 B
X NC 32 -300 -2050 100 U 50 50 1 1 N N
X CABLE_DETECT 33 900 -1300 100 L 50 50 1 1 I
X R_DNP_VCC 33 -1000 -700 100 R 50 50 1 1 P
X NC 35 -400 -2050 100 U 50 50 1 1 N N
X VDDA 36 -300 1200 100 D 50 50 1 1 W
X VDD 37 300 1200 100 D 50 50 1 1 W
X VDD 38 400 1200 100 D 50 50 1 1 W
X VDDA 39 -400 1200 100 D 50 50 1 1 W
X VSYNC 4 900 -800 100 L 50 50 1 1 O
X VDD 40 500 1200 100 D 50 50 1 1 W
X VDDA_VGA 41 900 -100 100 L 50 50 1 1 W
X GND 42 0 -2050 100 U 50 50 1 1 W
X VDD 43 600 1200 100 D 50 50 1 1 W
X VDDA 44 -500 1200 100 D 50 50 1 1 W
X VDDA 45 -600 1200 100 D 50 50 1 1 W
X VDD 46 700 1200 100 D 50 50 1 1 W
X VDDA 47 -700 1200 100 D 50 50 1 1 W
X C_100n_GND 48 -1000 -1500 100 R 50 50 1 1 P
X VDD_VGA_ref 49 900 0 100 L 50 50 1 1 I
X VDDA 5 -100 1200 100 D 50 50 1 1 W
X R_5.6k_GND 50 -1000 -900 100 R 50 50 1 1 P
X R 51 900 -300 100 L 50 50 1 1 O
X VDD_VGA 52 900 100 100 L 50 50 1 1 W
X G 53 900 -400 100 L 50 50 1 1 O
X B 54 900 -500 100 L 50 50 1 1 O
X GND 55 0 -2050 100 U 50 50 1 1 W N
X VDDA 56 -800 1200 100 D 50 50 1 1 W
X R_10k_GND 6 -1000 -1300 100 R 50 50 1 1 P
X NC 7 -100 -2050 100 U 50 50 1 1 N N
X VDD 8 200 1200 100 D 50 50 1 1 W
X SCK 9 900 600 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
......@@ -458,18 +458,4 @@ X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VDD
#
DEF power_VDD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VDD" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VDD 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library
src/fl2k.kicad_pcb
View file @ 93849459
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src/fl2k.pro
View file @ 93849459
update=22/05/2015 07:44:53
update=Wed 29 May 2019 01:38:46 PM CEST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
......@@ -31,3 +12,237 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=../assets/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
src/fl2k.sch
View file @ 93849459
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